/* Copyright (C) 2016 RDA Technologies Limited and/or its affiliates("RDA").
* All rights reserved.
*
* This software is supplied "AS IS" without any warranties.
* RDA assumes no responsibility or liability for the use of the software,
* conveys no license or title under any patent, copyright, or mask work
* right to the product. RDA reserves the right to make changes in the
* software without notification.  RDA also make no representation or
* warranty that such application will be suitable for the specified use
* without further testing or modification.
*/


#ifndef _DEBUG_HOST_INTERNALS_ASM_H_
#define _DEBUG_HOST_INTERNALS_ASM_H_

//THIS FILE HAS BEEN GENERATED WITH COOLWATCHER. PLEASE EDIT WITH CARE !

#ifndef CT_ASM
#error "You are trying to use in a normal C code the assembly H description of 'debug_host_internals'."
#endif

#include "globals_asm.h"


//==============================================================================
// debug_host_internal_registers
//------------------------------------------------------------------------------
///
//==============================================================================
#define REG_INT_REG_DBG_HOST_BASE  0x00000000

#define REG_INT_REG_DBG_HOST_BASE_HI BASE_HI(REG_INT_REG_DBG_HOST_BASE)
#define REG_INT_REG_DBG_HOST_BASE_LO BASE_LO(REG_INT_REG_DBG_HOST_BASE)

#define REG_INT_REG_DBG_HOST_CTRL_SET REG_INT_REG_DBG_HOST_BASE_LO + 0x00000000
#define REG_INT_REG_DBG_HOST_CTRL_CLR REG_INT_REG_DBG_HOST_BASE_LO + 0x00000001
#define REG_INT_REG_DBG_HOST_CLKDIV REG_INT_REG_DBG_HOST_BASE_LO + 0x00000002
#define REG_INT_REG_DBG_HOST_CFG   REG_INT_REG_DBG_HOST_BASE_LO + 0x00000003
#define REG_INT_REG_DBG_HOST_CRC_REG REG_INT_REG_DBG_HOST_BASE_LO + 0x00000004
#define REG_INT_REG_DBG_HOST_H2P_STATUS REG_INT_REG_DBG_HOST_BASE_LO + 0x00000005
#define REG_INT_REG_DBG_HOST_P2H_STATUS REG_INT_REG_DBG_HOST_BASE_LO + 0x00000006
#define REG_INT_REG_DBG_HOST_AHB_SYS_HMBURSREQ REG_INT_REG_DBG_HOST_BASE_LO + 0x00000007
#define REG_INT_REG_DBG_HOST_AHB_SYS_HMGRANT REG_INT_REG_DBG_HOST_BASE_LO + 0x00000008
#define REG_INT_REG_DBG_HOST_AHB_SYS_HSEL REG_INT_REG_DBG_HOST_BASE_LO + 0x00000009
#define REG_INT_REG_DBG_HOST_AHB_SYS_HSREADY REG_INT_REG_DBG_HOST_BASE_LO + 0x0000000A
#define REG_INT_REG_DBG_HOST_AHB_BB_MASTER REG_INT_REG_DBG_HOST_BASE_LO + 0x0000000B
#define REG_INT_REG_DBG_HOST_AHB_BB_HSREADY REG_INT_REG_DBG_HOST_BASE_LO + 0x0000000C
#define REG_INT_REG_DBG_HOST_AHB_BB_HSEL REG_INT_REG_DBG_HOST_BASE_LO + 0x0000000D
#define REG_INT_REG_DBG_HOST_AHB_SYS_MASK_SPLIT REG_INT_REG_DBG_HOST_BASE_LO + 0x0000000E
#define REG_INT_REG_DBG_HOST_AHB_BB_MASK_SPLIT REG_INT_REG_DBG_HOST_BASE_LO + 0x0000000F

//CTRL_SET
#define DEBUG_HOST_INTERNAL_REGISTERS_DEBUG_RESET (1<<0)
#define DEBUG_HOST_INTERNAL_REGISTERS_XCPU_FORCE_RESET (1<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_FORCE_WAKEUP (1<<2)
#define DEBUG_HOST_INTERNAL_REGISTERS_FORCE_BP_XCPU (1<<3)
#define DEBUG_HOST_INTERNAL_REGISTERS_FORCE_BP_BCPU (1<<4)
#define DEBUG_HOST_INTERNAL_REGISTERS_IT_XCPU (1<<5)
#define DEBUG_HOST_INTERNAL_REGISTERS_IT_BCPU (1<<6)
#define DEBUG_HOST_INTERNAL_REGISTERS_DEBUG_PORT_LOCK (1<<7)

//CTRL_CLR
//#define DEBUG_HOST_INTERNAL_REGISTERS_XCPU_FORCE_RESET (1<<1)
//#define DEBUG_HOST_INTERNAL_REGISTERS_FORCE_WAKEUP (1<<2)
//#define DEBUG_HOST_INTERNAL_REGISTERS_FORCE_BP_XCPU (1<<3)
//#define DEBUG_HOST_INTERNAL_REGISTERS_FORCE_BP_BCPU (1<<4)
//#define DEBUG_HOST_INTERNAL_REGISTERS_DEBUG_PORT_LOCK (1<<7)

//CLKDIV
#define DEBUG_HOST_INTERNAL_REGISTERS_CFG_CLK(n) (((n)&0x3F)<<0)

//CFG
#define DEBUG_HOST_INTERNAL_REGISTERS_DISABLE_UART_H (1<<0)
#define DEBUG_HOST_INTERNAL_REGISTERS_DISABLE_IFC_H (1<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_DEBUG_HOST_SEL (1<<2)
#define DEBUG_HOST_INTERNAL_REGISTERS_FORCE_PRIO_H (1<<7)

//CRC_REG
#define DEBUG_HOST_INTERNAL_REGISTERS_CRC (1<<0)
#define DEBUG_HOST_INTERNAL_REGISTERS_FC_FIFO_OVF (1<<1)

//H2P_STATUS
#define DEBUG_HOST_INTERNAL_REGISTERS_STATUS(n) (((n)&0xFF)<<0)

//P2H_STATUS
//#define DEBUG_HOST_INTERNAL_REGISTERS_STATUS(n) (((n)&0xFF)<<0)

//AHB_SYS_HMBURSREQ
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_IFC_HMBURSREQ (1<<0)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_DMA_HMBURSREQ (1<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_AHB2AHB_HMBURSREQ (1<<2)
#define DEBUG_HOST_INTERNAL_REGISTERS_XCPU_HMBURSREQ (1<<3)
#define DEBUG_HOST_INTERNAL_REGISTERS_USBC_HMBURSREQ (1<<4)
#define DEBUG_HOST_INTERNAL_REGISTERS_GOUDA_HMBURSREQ (1<<5)

//AHB_SYS_HMGRANT
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_IFC_HMGRANT (1<<0)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_DMA_HMGRANT (1<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_AHB2AHB_HMGRANT (1<<2)
#define DEBUG_HOST_INTERNAL_REGISTERS_XCPU_HMGRANT (1<<3)
#define DEBUG_HOST_INTERNAL_REGISTERS_USBC_HMGRANT (1<<4)
#define DEBUG_HOST_INTERNAL_REGISTERS_GOUDA_HMGRANT (1<<5)

//AHB_SYS_HSEL
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_MEM_EXT_HSEL (1<<0)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_MEM_INT_HSEL (1<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_IFC_HSEL (1<<2)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_AHB2AHB_HSEL (1<<3)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_USBC_HSEL (1<<4)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_GOUDA_HSEL (1<<5)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_XCPU_RAM_HSEL (1<<6)

//AHB_SYS_HSREADY
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_IFC_HSREADY (1<<0)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_MEM_HSREADY (1<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_AHB2AHB_HSREADY (1<<2)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_USBC_HSREADY (1<<4)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_GOUDA_HSREADY (1<<5)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_XCPU_RAM_HSREADY (1<<6)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_HREADY (1<<7)

//AHB_BB_MASTER
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_IFC_HMBURSREQ (1<<0)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_VOC_HMBURSREQ (1<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_AHB2AHB_HMBURSREQ (1<<2)
#define DEBUG_HOST_INTERNAL_REGISTERS_BCPU_HMBRSREQ (1<<3)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_IFC_HMGRANT (1<<4)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_VOC_HMGRANT (1<<5)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_AHB2AHB_HMGRANT (1<<6)
#define DEBUG_HOST_INTERNAL_REGISTERS_BCPU_HMGRANT (1<<7)

//AHB_BB_HSREADY
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_MEM_HSREADY (1<<0)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_VOC_HSREADY (1<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_SRAM_HSREADY (1<<2)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_IFC_HSREADY (1<<3)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_AHB2AHB_HSREADY (1<<4)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_HREADY (1<<7)

//AHB_BB_HSEL
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_MEM_EXT_HSEL (1<<0)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_MEM_INT_HSEL (1<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_VOC_HSEL (1<<2)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_SRAM_HSEL (1<<3)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_IFC_HSEL (1<<4)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_AHB2AHB_HSEL (1<<5)

//AHB_SYS_MASK_SPLIT
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_SYS_MID_BIST (1<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_SYS_MID_DMA (1<<2)
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_SYS_MID_XCPU (1<<3)
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_SYS_MID_AHB2AHB (1<<4)
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_SYS_MID_IFC (1<<5)
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_SYS_MID_USB (1<<6)
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_SYS_MID_GOUDA (1<<7)
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_SYS_MID_VOC (1<<8)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_MASK_SPLIT(n) (((n)&0xFF)<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_MASK_SPLIT_MASK (0xFF<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_SYS_MASK_SPLIT_SHIFT (1)

//AHB_BB_MASK_SPLIT
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_BB_MID_BIST (1<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_BB_MID_IFC (1<<2)
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_BB_MID_VOC (1<<3)
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_BB_MID_BCPU (1<<4)
#define DEBUG_HOST_INTERNAL_REGISTERS_MASK_SPLIT_BB_MID_AHB2AHB (1<<5)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_MASK_SPLIT(n) (((n)&31)<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_MASK_SPLIT_MASK (31<<1)
#define DEBUG_HOST_INTERNAL_REGISTERS_BB_MASK_SPLIT_SHIFT (1)




#endif
